This invention relates to pulse detection circuitry and more particularly to such circuitry for detection of slip conditions between various input signals.
There are many situations in which it is important to know if the digital pulses on a particular signal line are in or out of synchronization with digital pulses on another signal line. Such situations occur in phase-locked loops and digital receivers. This situation also occurs when two circuits are operating independent from, but in parallel to, each other, with both circuits operating from the same master clock, from the same clock frequency or from independent master clocks which are expected to be at the same frequency. Typically, information must be transferred between such circuits and thus it is important that both circuits be in synchronization with each other. Conditions lacking synchronization must be quickly detected so that corrective action can be taken.
The problem is compounded when the signals that are being monitored are asynchronous with respect to each other and may have a wide range of duty cycles or possibly a dynamically varying duty cycle.
Circuits are available to accomplish the desired result; examples being U.S. Pat. Nos. 4,471,299 and 4,516,250 and the circuit discussed in an article entitled "Cycle Slip Detector" by F. M. Gardner in the September 1977 issue of IEEE Transactions on Instrumentation and Measurement (Vol. 1M-26, No. 3). However, such circuits rely on processing the asynchronous signals throughout the detection circuitry. While such circuits are workable, the asynchronous nature of their design poses difficulties in testing and in using VLSI techniques for implementation. This arises because such circuits typically have digital one-shots or delay lines. By comparison with synchronous logic circuits, these components are always more difficult to verify and to generate manufacturing tests. In addition, they are not easily adapted to VLSI implementation. The output of such circuits may also be asynchronous, imposing the same difficulties to further signal processing.
The advantages of predominately synchronous operation are straight forward implementation in VLSI, simplified circuit design, and a simplified manufacturing test.